1. Field of Invention
The present invention relates to a method for testing reliability of a self-aligned silicide process. More particularly, the present invention relates to a method for testing a leakage current caused by self-aligned silicide, using different test structures after a self-aligned silicide process.
2. Description of Related Art
In a conventional method for testing reliability of a self-aligned silicide process, test structures, as shown in FIG. 1 and FIG. 2, are commonly deposited on wafer scribe lines. These test structures include a big diffusion region 102 (FIG. 1), or multiple bars of diffusion regions 102 on the wafer 100 (FIG. 2), and a metal silicide layer 104 thereon. These test structures and a metal-oxide semiconductor (MOS) transistor in a chip are simultaneously formed, therefore, the test structures can monitor reliability of the self-aligned silicide layer on a source/drain region of the MOS transistor to avoid malfunction of the MOS transistor. The two test structures (shown in FIG. 1 and FIG. 2) are designed according to a leakage current occurring from the metal silicide layer to the junction, and a leakage current occurring at the edge of the metal silicide layer. Therefore, design parameters of the two test structures in FIGS. 1 and 2 include area and perimeter of the metal silicide layer.
Accordingly, the conventional method for testing reliability of a self-aligned silicide process is to measure a current of the test structure shown in FIG. 1 or FIG. 2, and then calculate current density from the metal silicide to the junction region and current density of the edge of the metal silicide. According to these two current densities, the leakage current caused by the metal silicide layer can be monitored. If the leakage current is not in an allowable range, the self-aligned silicide process has to be immediately rectified so as to reduce wafer nullity probability.
However, when the test structures shown in FIG. 1 and 2 are employed in 0.25 .mu.m semiconductor processes, some problems arise. The device malfunction probability is still large when testing for device electricity after the whole semiconductor processes, even though the test result of the self-aligned process is favorable. In other words, the conventional test structure cannot accurately monitor the reliability of the self-aligned process. This leads to an increase of the wafer malfunction probability and capital expenditure.